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ASIC Verification Engineer

ASIC Verification Engineers are responsible to implement test plans to verify units in a subsystem chip level functionality environment, verifying peripherals such as PCIe, SATA, USB, MIPI protocols, analog mixed signal verification such as PHY verification, AMBA protocols, RTL. OOP experience for test planning, debugging adversarial testing Utilize HVL Vera, Specman, System Verilog, OVM, Verilog or VHDL C/C++, Tcl,Perl

Location:
Santa Clara, CA

Requirements:

  • Bachelor of Science in Electrical Engineering
  • 5 years of experience

Email resumes to: janderson@technical-link.com