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Mask Design Engineer

Skills/Experience:

7 to 10 years of RF/Analog Layout Design Experience Basic understanding of semiconductor devices as well as CMOS 65nm, 40nm and 28nm TSMC processes. 7 Years of Cadence VXL tools experience 7 years of Mentor Calibre verification tool experience Cadence 6.1.5 OA is a plus. Excellent communication skills and ability to work within a team environment.

Location: San Diego, CA or Santa Clara, CA

Email resumes to: janderson@technical-link.com