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ASIC Design Engineer


Perform RTL design changes and validation ( RTL/Gate Simulation) - Take ownership of running all design checking tools and make sure the design is clean of any issues - Perform synthesis and timing analysis - Drive test plan and verification of IP block -Communication with top level team to support implementation tasks.


Good understanding of Digital design (familiar with VHDL and Verilog) Familiar with RTL DRC Tools: - Spyglass for (linting , DFT, DFTDSM) - Clock domain crossing (CDC) - Conformal Low Power (CLP ) Familiar with synthesis and STA flow (Synopsys) Have good debugging/problem solving experiences Must have simulation experience (VCs, write tests , debug waveforms ) Have good communication skills Programming languages: VHDL, Verilog, Perl, C, C++, C-shell, UNIX.

Location: San Diego, CA

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