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Physical Design Engineer


Experience and knowledge of tools for physical design implementation (Floorplanning, CTS, P&R, STA) for CPUs and GPUs in advanced technologies like 45nm and 28nm CMOS. - Additional expertise in one or more of the following areas: - STA tool and timing closure methodologies - Developing and implementing timing ECOs including affect on congestion/routing/power - Power grid, clock tree, and low-power reduction implementation methods - Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing - Floorplanning, Placement, CTS, P&R - Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification - Programming and scripting skills (Tcl, perl and/or C) - Strong verbal and written communication skills


You will be part of a team responsible for the complete Physical Design Flow for MSM/MDM/CSM chips. Tasks involved can be one or more of the following: -Working with the RTL design team on understanding design in context of physical design timing closure including development of timing constraints required for implementation. -Working with the DFT team on understanding DFT design in regards to physical design timing closure. -Leading core and Top level timing closure activities. -Developing new scripts/flows to improve the timing closure process. -Part of a team responsible for the complete Physical Implementation of cores i.e. graphics, video, multimedia, processor, DDR -Enablement of low power implementation methods -Core and Top level Floorplanning, placement, CTS, P&R, PV, and Signal Integrity Analysis -Development of high speed customized logic cells

Location: San Diego, CA or San Jose, CA

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